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W631GG6KB
10.16 AC Characteristics
10.16.1 AC Timing and Operating Condition for -11 speed grade
SYMBOL
SPEED GRADE
PARAMETER
DDR3-1866 (-11)
MIN. MAX.
UNITS
NOTES
Common Notes
Clock Input Timing
1, 2, 3, 4
t CK ( DLL -off)
Minimum clock cycle time (DLL-off mode)
8
?
nS
45
t CK (avg)
Average Clock Period
See ―Speed Bin‖ on page 13 6
pS
t CH (avg)
t CL (avg)
Average CK/CK# high pulse width
Average CK/CK# low pulse width
0.47
0.47
0.53
0.53
t CK (avg)
t CK (avg)
t CK (abs)
Absolute Clock Period
Min.: t CK (avg)min + t JIT (per)min
Max.: t CK (avg)max + t JIT (per)max
pS
37
t CH (abs)
t CL (abs)
t JIT (per)
t JIT (per,lck)
Absolute CK/CK# high pulse width
Absolute CK/CK# low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
0.43
0.43
-60
-50
?
?
60
50
t CK (avg)
t CK (avg)
pS
pS
38
39
t JIT (cc)
t JIT (cc,lck)
t JIT (duty)
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking
period
Clock Duty Cycle Jitter
120
100
Already included in t CH (abs) and
t CL (abs)
pS
pS
pS
t ERR (2per)
t ERR (3per)
t ERR (4per)
t ERR (5per)
t ERR (6per)
t ERR (7per)
t ERR (8per)
t ERR (9per)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
-88
-105
-117
-126
-133
-139
-145
-150
88
105
117
126
133
139
145
150
pS
pS
pS
pS
pS
pS
pS
pS
t ERR (10per) Cumulative error across 10 cycles
t ERR (11per) Cumulative error across 11 cycles
t ERR (12per) Cumulative error across 12 cycles
-154
-158
-161
154
158
161
pS
pS
pS
t ERR (nper)
Cumulative error across n = 13, 14...49, 50
cycles
Min.: t JIT (per)min * (1 + 0.68 * ln(n))
Max.: t JIT (per)max * (1 + 0.68 * ln(n))
pS
7
Publication Release Date: Dec. 09, 2013
Revision A05
- 138 -
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